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Sunday, May 7, 2017

Master Slave D Flip Flop Verilog Code

MASTER SLAVE D FLIP FLOP

In SR flip flop when the conditions SET and RESET both are 1 the that condition is known as forbidden condition. This tries to change the both Q and Q’ to be 1 and whichever will turn 1 first will further control the latch which is certainly we don’t want. This can be avoided when both S and R inputs are short circuited with a not gate in between. This prevents the forbidden condition of S and R to be 1. This combination is what we call D – Flip Flop. Thus we require only single data known as D for this FF. The output Q changes whenever D is applied with any input bit.
Whenever the clock goes from low to high i.e. posedge the input is read and fed to the output. Whenever the clock goes from high to low i.e. negedge the previous output is retained back or in easy words it remains the same.


The basic D Flip Flop is improved using a Master Slave condition. Here two D flip flops are used and the clock of Master D FF is inverted and then fed to the clock of the Slave D FF. The output Q of Master FF is fed to the input D of Slave FF. Thus when clock goes low to high the Master reads the input and stores the output. During this phase the Slave FF remains locked.


When the clock goes from High to low the Slave FF gets activated and the Master gets locked. Since during negede Master retains the output thus it acts as input for Slave and output is obtained. Master Slave condition is used because it avoids the race around condition of toggling output multiple times in a single clock cycle.

Code for Master Slave D type FF

module Mas(d,reset,clk,q,qbar);
 input d,clk,reset;
 output q,qbar;
 Master Masterr(d,reset,clk,qx,qbarx);
 Master Slave(qx,reset,!clk,q,qbar);
endmodule

module Master(d,reset,clk,q,qbar);
 input d,reset,clk;
 output reg q,qbar;
 initial
  q = 0;
 always @(posedge clk)begin
  if(~reset)begin
   q <= d;
   qbar <= !d;
  end
  else begin
   q <= 1'bx;
   qbar <= 1'bx;
 end
 end
endmodule

Testbench for Master Slave D FF

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Shashi Suman
//
// Create Date:   19:30:41 05/12/2025
// Design Name:   Mas
// Module Name:   F:/Season 1/Master/TestMas.v
// Project Name:  Master
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Mas
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TestMas;

// Inputs
reg d;
reg reset;
reg clk;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)
Mas uut (
.d(d), 
.reset(reset), 
.clk(clk), 
.q(q), 
.qbar(qbar)
);

initial begin
// Initialize Inputs
clk = 0;
fork
#10 d = 1;
#25 reset = 1;
#35 reset = 0;
#50 d = 0;
join
end
   always #2 clk = !clk;   
endmodule

Output Waveform of Master Slave D FF









Block Diagram of Master Slave D FF

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