Verilog Code for MOD 5 Counter

As discussed in the previous post, I implemented the MOD4 and MOD 8 Counters. In this, I'll implement MOD 5 Counter. This counter will have 5 states starting from 000 to 100 and then again back to zero. However, according to the equation below,
                                                                                    N <= 2n
you might find it vague. I mean 5 is not a power of 2. So how is it possible to design a counter which will count a non-power of 2? If you guessed by using external circuitry, then you are absolutely correct. Within this type of counters, we will have D Flip-Flops with clear flags. By intuition, we can say that just after 100, we will have to somehow clear the flip-flops' values, thus bringing the values back to zero. To calculate the minimum number of gates, we will have to use the same equation.  This gives the value of n as 3. Hence, we will have to have 3 D flip-flops to count 5 states in order to satisfy the requirements of MOD 5 counter.…

Verilog Code for MOD Counters

Counters are used to count and move the state of a circuit from one state to another. Whenever they are given a clock signal, either the system moves one state ahead or behind. It is not necessary to jump only one state. We can jump by a number of steps but for that, we would require circuitry. Counters are examples of sequential circuits. It requires a clock signal to function and states are changed at either positive edge of the negative edge of the clock. It is important to decide on the type of counter. We can design either an asynchronous counter or a synchronous counter. In an asynchronous counter, only the first flip-flop is dependent on the clock. The output of the first-floor shop act as a clock to the second flip-flop. Similarly,  the output of the second flip-flipflop will act as the clock for the third flip-flop and it goes on. On the other side in a synchronous counter, each flip-flop receives the clock signal at the same time. So we can conclude that asynchronous counte…

Setup Time and Hold Time

Setup time and Hold time are very important concepts when designing circuits. Compromising with these parameters would give an organized output. Whenever we see a circuit, we see it switching instantly ON and instantly OFF. It just appears like teleportation. Electronics from the low state were teleported to a higher state and vice versa. However, teleportation never occurs in electronics. No matter how fast switching circuits has been invented, it will always take some amount of time. Switching a circuit from LOW to HIGH does involve time. The time involved is as small as nanoseconds or picoseconds.
Setup Time: The minimum time required to keep the input data stable while the clock has started to change is called Setup Time. Any change or malfunction of data within this period leads to Setup Violations.
Hold Time: The minimum time required to keep the input data stable after the clock transition has taken place is called Hold Time. Any change or malfunction of data within this perio…

Verilog simulation in Xilinx

Hi  In this post, I am going to show you how to simulate a Verilog code in Xilinx ISE. I have included every step with an image so that the user can easily understand every step clearly. 
Ok let's begin  I am using Xilinx ISE version 14.2  You can have your own version of Xilinx or ModelSim or MultiSim HDL Simulator but the methodologies for implementing a Verilog code within them might be different. 
For this post its version 14.2 

First of all click on the desktop icon ISE Design Suite 14.2 

A Window will open. After the window opens, which might take some time depending on your system configuration. Click on the tab "New Project" as shown below. 

Enter the name of the project in the first field. Be sure that the location where you are going to save your project is having permission to write. You cannot save at a location that has only read only permission.  Click "Next" and select the "Device" field as Spartan 6 because that's what I am going …

Neural Network: Part 2

Neural Network: Logistic Regression In this post, I'll deal with logic regression and its implementation of a single neuron network. I hope you have read my previous post on mattresses and its operation using NumPy package. You can click here to go to my previous post 
Logistic regression basically computes the probability of the output to be one. For example, if we train our Logistic model to recognize the image of a dog then for any new image the model basically try to calculate the probability of whether the new image is a dog or not. the higher the probability will imply that the given image is of a dog. 
A neuron is the primary and fundamental unit of computation for any neural network. A neuron will receive a vector that will include the input features. Each of the features will get multiplied with their corresponding weights and then a bias will be added to each of the features after which the weighted sum will be calculated. This will produce a linear output from the prev…