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Showing posts from April, 2017

### Verilog Code for I2C Protocol

[VISIT NEW POST FOR I2C HERE ] I2C PROTOCOL HolaAmigos
I2C devices have been around us for a long time. If you have done any Arduino projects with any peripherals such as Bluetooth (HC-05) or Gyroscope (MPU6050) or Barometer etc you might be surprised you have already used I2C devices. Yes
An I2C basically consists of a master microcontroller and a slave device which responds to the requests of the master. A slave cannot operate on its own. It can't even communicate with other slaves without having any permission from the master.
You may have come across multi-master schematic but it becomes much more complex to handle such situation because of data leakage and also it requires more than 1 microcontrollers. So if you are using an I2C you cannot use any other non-I2C device on the same bus as both SDA and SCL lines are in conjunction with the I2C module. If you find this facility somewhere you are being fooled seriously !!!  I2C works on 2 signals as SCL and SDA                   …

### Verilog Code for Sequence Detector

SEQUENCE DETECTOR Hola Amigos Beginning with the simple theory about Sequence Detector. A sequence detector an algorithm which detects a sequence within a given set of bits. Of course the length of total bits must be greater than sequence that has to be detected. Sequence detector basically is of two types –

a.Overlapping b.Non Overlapping In overlapping some of the last bits can also be used for the start of detection of next sequence within the given bits.

For Example Let the sequence be 11011 and given bits 1101101101101101 Now lets work on overlapping concept. We have 5 bits here in 11011 hence we will have 5 states. Let em be A/B/C/D and E. Initially pstate will be A. Now
1.Incoming bit is 1 (from 1101101101101101) and it matches with first bit of sequence hence jump to next B. Requirement(1011) 2.Incoming bit is 1 (from 1101101101101101)and it matches with  first bit of requirement hence jump to state C. Requirement (011) 3.Incoming bit is 0 (from 1101101101101101) and it matches with fir…

### Verilog code for BCD to 7 Segment Display

BCD TO 7-SEGMENT DISPLAY Hola Amigos BCD stands for Binary Coded Decimal which runs only till 9. The main objective is to convert the binary input to a decimal number to be displayed on 7-Segment Block which looks like this

Here is the truth table for this
"s" Represents State and A-G represents pins of 7-Seg Display
Here is the code
module bcd(a,b,c); input [3:0]a;  // the number wire [3:0]a; output [6:0]b; reg [6:0]b; output [6:0]c; reg [6:0]c; always @(a) begin if(a==0)begin b = 7'b1111110;          // in terms of 7-Seg "abcdefg" i.e Here a/b/c/d/e/f are on i.e "1" and G is off "0" c = 7'b0000000;         // for this pattern we have output as zero end else if(a==1)begin b = 7'b0110000; c = 7'b0000001; end else if(a==2)begin b = 7'b1101101; c = 7'b0000010; end else if(a==3)begin b = 7'b1111001; c = 7'b0000011; end else if(a==4)begin b = 7'b0110011; c = 7'b0000100; end else if(a==5)begin b = 7'b1011011; c = 7'b0000101; end else if(a==…

### Verilog Code for Asynchronous Counters

ASYNCHRONOUS COUNTER
Asynchronous means in terms of simple definition without external clock synchronization. The output always remains free from clock signal.       Generally the first FF is clocked with main external clock and each of next FF have output of previous FF as their clock. This helps in reducing the number of FFs and additional gates hence requires less complexity.     Now coming to the special "MOD" term. It basically stands for modulus.
When you have to design a Mod-Y counter then the basic steps include 1. The equation -: 2x = Y.  2.  Now find value of X if you know basic Maths. You can use logarithms
Thus after getting the value of X you basically get how many FFs are required hence you require X FFs to design Mod- Y UP or Down counter.
Here is the block diagram of Mod-16 or 4bit Asynchronous Counter

Now For Mod-16 we have value of X as 4 hence 4 FFs
Here is the code to test this

module dff(d,clk,q); input d; input clk; wire d; wire clk; output q; reg q; initial q = 1'b0;