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System Verilog Inheritance

System Verilog InheritanceSystem Verilog supports OOPS Inheritance which allows a user to inherit the class properties including the task, functions as well variables. System Verilog supports single inheritance as well as multiple inheritance.
Elaboration - Consider a case where we have declared a class named parentand we wantto its properties to be shared with other classes in the module or program too. Obviously re-writing the code with properties inside each child class will come first in our mind but that doesn’t sound great. It will certainly consume more script data and time too. So to cover this idea is what inheritance is all about.
Example – Your family has your Dad, Mom, son and a little daughter. So your Dad ( or your Mom ) is our Parent Class. You and your sister are the child classes inheriting from Parent Class. Since both children possess habits and behavior of parents. The habits and behavior are the methods that have been inherited from the parents (Parent Class).
Okay…