# Frequency Divider D Flip Flop Verilog Code

## FREQUENCY DIVIDER USING D FLIP FLOP

D FF can also be used as a frequency divider where the output frequency becomes exact half to the frequency of the clock signal provided to the D FF. It can be used as a binary divider or “divided by 2” format. This is done by short circuiting the Q’ output and input D. Thus once initiated it works like a charm. It can be also refered as “divided by 2” or binary divider. Amazing fact is that by placing the feedback around D FF we get another FF called as T FF or basically saying Toggle Bistable Flip Flop.

FF Code for frequency divider

module Mas(d,reset,clk,q,qbar);
input d,clk,reset;
output q,qbar;
Master Slave(qbar,reset,!clk,q,qbar);
endmodule

module Master(d,reset,clk,q,qbar);
input d,reset,clk;
output reg q,qbar;
initial begin
q = 0;
qbar = 1;
end
always @(posedge clk)begin
if(~reset)begin
q <= d;
qbar <= !d;
end
else begin
q <= 1'bx;
qbar <= 1'bx;
end
end
endmodule

Code for TestBench

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Shashi Suman
//
// Create Date:   19:30:41 05/07/2017
// Design Name:   Mas
// Module Name:   F:/Season 1/Master/TestMas.v
// Project Name:  Master
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Mas
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
//
////////////////////////////////////////////////////////////////////////////////

module TestMas;

// Inputs
reg reset;
reg clk;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)
Mas uut (
.d(d),
.reset(reset),
.clk(clk),
.q(q),
.qbar(qbar)
);

initial begin
// Initialize Inputs
clk = 0;
fork
reset = 0;
join
end
always #2 clk = !clk;
endmodule

Output Waveform
Observe carefully how the output Q and Q' have a low frequency with that of the clock.

The Block Model of divider

To further divide frequency click here

So Long