# Verilog Code for 8bit Full Adder

##

FULL ADDER

Hola Amigos

Adders as we all have used might pose a problem when simulated for very long space complex projects as the results of full adder are not instant. It does take time and the propagation delay increases with time so how do we deal with delay caused by each gate. Here have a look on this basic adder

Adders as we all have used might pose a problem when simulated for very long space complex projects as the results of full adder are not instant. It does take time and the propagation delay increases with time so how do we deal with delay caused by each gate. Here have a look on this basic adder

What we come to know about it is that for C4 we have to wait for C3, similarly for C3 we have to wait for C2. This causes delay and then there comes Carry Look Ahead Adder in limelight.

One can increase the space complexity of the code to decrease the time for propagation or introduce just faster delays to decrease the propagation delay of the overall adder.

A basic full adder is a parallel adder which is based on complex circuit to directly induce the carry from the inputs provided.

Now S = Sum and C(-1) = carry from previous addition.

So S = EXOR(A,B,C) and

C(0) = A.B + EXOR(A,B).C(-1)

Now let A.B = G

_{i }and EXOR(A,B) = P_{i }
So C

_{0 }= G_{0}+ P_{0 }. C_{-1 }
C

_{1 }= G_{1}+ P_{i }. C_{0}
C

_{2 }= G_{2}+ P_{i }. C_{1}
C

_{3 }= G_{3}+ P_{i }. C_{2}
C

_{4 }= G_{4}+ P_{i }. C_{2}####
SUM = A’B’C_{in} + A’BC’_{in } + AB’C’_{In} + ABC_{in }
C_{out} = BC_{in } + AC_{in} + AB

_{in}+ A’BC’

_{in }+ AB’C’

_{In}+ ABC

_{in }

_{out}= BC

_{in }+ AC

_{in}+ AB

#### Code for a 8 bit Full Adder

module FA(a,b,c,s,co);

input [7:0]a,b;

output [8:0]s;

output co;

input c;

Carry c1(a[0],b[0],c,s[0],cx0);

Carry c2(a[1],b[1],cx0,s[1],cx1);

Carry c3(a[2],b[2],cx1,s[2],cx2);

Carry c4(a[3],b[3],cx2,s[3],cx3);

Carry c5(a[4],b[4],cx3,s[4],cx4);

Carry c6(a[5],b[5],cx4,s[5],cx5);

Carry c7(a[6],b[6],cx5,s[6],cx6);

Carry c8(a[7],b[7],cx6,s[7],s[8]);

assign co = s[8];

endmodule

module Carry(a,b,c,s,co);

input a,b;

input c;

output s,co;

wire out4;

wire out6;

and (out1,a,b);

xor (out2,a,b);

and (out3,out2,c);

or (out4,out3,out1);

assign co = out4;

xor (out5,a,b);

xor (out6,out5,c);

assign s = out6;

endmodule

input [7:0]a,b;

output [8:0]s;

output co;

input c;

Carry c1(a[0],b[0],c,s[0],cx0);

Carry c2(a[1],b[1],cx0,s[1],cx1);

Carry c3(a[2],b[2],cx1,s[2],cx2);

Carry c4(a[3],b[3],cx2,s[3],cx3);

Carry c5(a[4],b[4],cx3,s[4],cx4);

Carry c6(a[5],b[5],cx4,s[5],cx5);

Carry c7(a[6],b[6],cx5,s[6],cx6);

Carry c8(a[7],b[7],cx6,s[7],s[8]);

assign co = s[8];

endmodule

module Carry(a,b,c,s,co);

input a,b;

input c;

output s,co;

wire out4;

wire out6;

and (out1,a,b);

xor (out2,a,b);

and (out3,out2,c);

or (out4,out3,out1);

assign co = out4;

xor (out5,a,b);

xor (out6,out5,c);

assign s = out6;

endmodule

#### Here is the Test Bench

module TestCarry;

// Inputs

reg [7:0] a;

reg [7:0] b;

reg c;

wire [8:0] s;

wire co;

CLA uut (

.a(a),

.b(b),

.c(c),

.s(s),

.co(co)

);

initial begin

// Initialize Inputs

a = 8'b01101010;

b = 8'b10111101;

c = 0;

end

endmodule

Here is the output in action

Here s[8:0] is the sum c is input carry co is the final carry a[7:0] and b[7:0] are the numbers

So Long

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