Verilog Code for Carry Look Ahead Adder
CARRY LOOK AHEAD ADDER
When full adders are
used they often introduce a time delay since every single bit addition depends
on the carry of previous addition. Hence C4 will wait for C3 and C3 will for C2
and so on.
A carry look ahead
adder basically reduces the time complexity however increases the gate complexity
as well as space complexity, hence its cost always increases. In CLA adder a concept
comes of Generate Carry and Propagate Carry. The Generate Carry is produced
when both of the A and B are 1 and it doesn’t depend on Ci at that moment.
The Propagate Carry is
produced when atleast one of A and B is 1 or whenever there is an input carry then
the input carry is propagated.
But why do we have “LOOK
AHEAD” here. It is because whenever two bits are gonna be added then Generate
and Propagate will determine whether the carry will generate of input carry
will propagate. Thus when no Propagation is required addition takes place
without waiting for the ripple carry
Thus to determine
Generate we have
Gi = Ai . Bi
To determine Propagate
we have
Pi = Ai EXOR Bi
Thus the basic equation
comes in detail as
Ci+1 = Gi
+ Pi . Ci
which gives all C[0],C[1],C[2],C[3] as
C[0] = Cin
C[1] = G[0] + ( P[0] & C[0] )C[2] = G[1] + ( P[1] & G[0] ) + ( P[1] & P[0] & Cin )
C[3] = G[2] + ( P[2] & G[1] ) + ( P[2] & P[1] & G[0] ) + ( P[2] & P[1] & P[0] & Cin );
Cout = G[3]+ ( P[3] & G[2] ) + ( P[3] & P[2] & G[1] ) + ( P[3] & P[2] & P[1] & G[0] ) + ( P[3] & P[2] & P[1] & P[0] & C[0] )
The sum is concat of Cout and P EXOR C
S = {Cout,P^C}
The Group Generate is
GG = P[0] & P[1] & P[2] & P[3]
The Propagate Group is
PG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);
When multiple CLA's are joined then the GG and PG of each group is used to determine input carry for the CLA's.
Code for 4 bit CLA
module CLA(a,b,ci,co,s);
input [3:0]a,b;
output [4:0]s;
input ci;
output co;
wire [3:0]G,P,C;
assign G = a&b;
assign P = a^b;
assign co=G[3]+ (P[3]&G[2]) + (P[3]&P[2]&G[1]) + (P[3]&P[2]&P[1]&G[0]) + (P[3]&P[2]&P[1]&P[0]&ci);
assign C[3]=G[2] + (P[2]&G[1]) + (P[2]&P[1]&G[0]) + (P[2]&P[1]&P[0]&ci);
assign C[2]=G[1] + (P[1]&G[0]) + (P[1]&P[0]&ci);
assign C[1]=G[0] + (P[0]&ci);
assign C[0]=ci;
assign s = {co,P^C};
endmodule
Code for Test Bench
module fi;
reg [3:0] a;
reg [3:0] b;
reg ci;
wire co;
wire [4:0] s;
CLA uut (
.a(a),
.b(b),
.ci(ci),
.co(co),
.s(s)
);
initial begin
// Initialize Inputs
a = 4'b1101;
b = 4'b1011;
ci = 0;
end
endmodule
Here is the output of CLA
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test bench was not working
ReplyDeleteWorking for me here
DeleteDo check that module name and instantiated module name inside test bench is same
My module name here is CLA
can you please provide CLA using PGcells
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