Skip to main content

Posts

Showing posts from June, 2017

Verilog Code for VGA Interface

Verilog Code for VGA Interface

VGA (Video Graphics Array) is a connection protocol used for display related activities and actions. It is basically the connection of cables to an output device. VGA are getting replaced by HDMI and micro HDMI cables but are still in use. A VGA connector pin has 15 connection pins. There are 3 rows with 5 pins each and a VGA adapter has same number of holes with same trapezoidal orientation to fit the VGA cable. A typical VGA interface runs on 25MHz. Since our FPGAs have 50MHz clock as default like I have on my Basys2, we have to reduce the clock to 25MHz. For that we will have to use clock divider. The frequency of 25Mhz is called pixel clock for a typical 640 X 320 display resolution. To interface we need to concentrate on some parameters like HS(Horizontal Sync), VS(Vertical Sync), RGB value. HS,VS ports are of 1 bit each. These are output ports. RGB is of 8 bits. First 3bits for RED, next 3 bits for GREEN and final 2 bits for BLUE. Now take an example of…

FPGA Simulation with Xilinx

How to simulate with FPGATo simulate your Verilog code you will need a FPGA. This tutorial willonly cover about simulating your program. Here are the things to gather up. FPGA Board USB Cable Xilinix ISim 14.2 or any version Burner Software from your respective FPGA Brand We are using here Diligent Basys2 FPGA and the software for its burning process is Diligent Adept. Now Open Xilinx ISim and create a new project. Click on the simulation radio button Right Click on the project and select new source. Click Verilog Module then choose your input outputs (can be set later also). After we finish write up your program. If you have a single module program without any instantiation then no need to make outer module. If you have many instantiation then make an outer module from where instantiation will take place joining all modules and will have the input and outputs which we want to see. Create a testbench for your top module. This is the hierarchy in Xilinx. Note here the top module, testbench.