FPGA Simulation with Xilinx

How to simulate with FPGA

To simulate your Verilog code you will need a FPGA. This tutorial willonly cover about simulating your program.
Here are the things to gather up.
  1. FPGA Board
  2. USB Cable
  3. Xilinix ISim 14.2 or any version
  4. Burner Software from your respective FPGA Brand
We are using here Diligent Basys2 FPGA and the software for its burning process is Diligent Adept.
  1. Open Xilinx ISim and create a new project.
  2. Click on the simulation radio button
  3. Right Click on the project and select new source.
  4. Click Verilog Module then choose your input outputs (can be set later also). After we finish write up your program.
  5. If you have a single module program without any instantiation then no need to make outer module.
  6. If you have many instantiation then make an outer module from where instantiation will take place joining all modules and will have the input and outputs which we want to see.
  7. Create a testbench for your top module.
This is the hierarchy in Xilinx. Note here the top module, testbench.
Now carefully jot down the following FPGA properties
  1. Family Sparttan ?? (Model)
  2. Device number
  3. Speed and
  4. Package
You can get all above information from the manufacturer of your FPGA board.
Now Right Click on your top hierarchy. It may appear with a format like this  “xc3s100e-4cp132”. It may vary for yours.
Then Select Design properties from the right click. Fill up the above collected details in this form.
For Basys2 its
  1. Family SPARTAN 3E
  2. Package CP132
  3. Device XC3S100E
  4. Speed -4
Click OK after entering all details.
Now click on implementation radio button.
One will find that hierarchy changes into the above image. Now Right Click your top module (here top.v) and click “Set as Top Module”. After this you would notice that a 3 square icon appears to the left of top module.
Watch the above image for it.

Post Listing

Right click the xc3s100e-4cp132”. And click new source and then navigate to “Implementation Constraint File”. Do this when simulation mode is selected.
Enter your file name and click next.
Note down your testbench i/o port names exactly.
Here input in clk and output is cath.
After entering name for your Implementation Constraint File a new blanck file will open with extension .ucf
The syntax for port listing is
NET <port name> LOC= <FPGA PORT> ;
In the field of port name enter your i/o ports in testbench.
Now on FPGA we have specific input ports and output ports. The input ports are switches and push buttons.
Notice below every switch there is an alphanumeric notation. Ex – N3,L2, F4, G3, B4, K3, L3, P11. Each switch is for 1 bit. Similarly push buttons have A7, M4 etc
These are the input ports.
For output we have LEDs just above the row of switches. Ex – G1, P4,N4 etc Each LED is for 1 bit output.
We have cath[6:0] as output and cannot be assigned on a single switch so here is the syntax for cath
net "cath<6>" loc = L14;
net "cath<5>" loc = H12;
net "cath<4>" loc = N14;
net "cath<3>" loc = N11;
net "cath<2>" loc = P12;
net "cath<1>" loc = L13;
net "cath<0>" loc = M12;
Here clk is the clock and for clock port B8 is reserved (on Basys2). So overall the entries goes like below
NOTE - These loc ports are of 7 segment display.
Now Click the top module with square icons (under implementation)
Click on the + hierarchy representing “Implement Design”. The click on Generate File. It will take time to do. When successful the result will be this.
Success- Got green tick marks. The question mark is with warnings so do check. Also when you find and error a red icon will appear as above. So do check. After completing all these steps connect the Basys2 with USB cable and open the program “Adept Diligent”
In the Connect menu Basys2 will appear automatically. Click on browse and locate to the project folder. You will find a file with extension .bit
Select that file. If something pops up accept it. Then click program and again a pop up would appear. Accept that and continue.
This will burn your program onto your FPGA and output will be shown on the LEDs.
We ran a program to display FPGA on seven segment mounted on board.
To switch and bit just turn the switch (UP=1 and DOWN=0)

For Push buttons when pushed will pass 1 else 0.

A counter program running on Basys2.

A counter program running on 7 segment display.

Feel Free to contact for any issues.
So Long.


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