Verilog Code for MOD Counters



Setup Time and Hold Time


Setup time and Hold time are very important concepts when designing circuits. Compromising with these parameters would give an organized output. Whenever we see a circuit, we see it switching instantly ON and instantly OFF. It just appears like teleportation. Electronics from the low state were teleported to a higher state and vice versa. However, teleportation never occurs in electronics. No matter how fast switching circuits has been invented, it will always take some amount of time.
Switching a circuit from LOW to HIGH does involve time. The time involved is as small as nanoseconds or picoseconds.



Setup Time:
The minimum time required to keep the input data stable while the clock has started to change is called Setup Time. Any change or malfunction of data within this period leads to Setup Violations.

Hold Time:
The minimum time required to keep the input data stable after the clock transition has taken place is called Hold Time. Any change or malfunction of data within this period leads to Hold Violations.


Below is the image how the human eye perceives a change in the clock signal



For the humans, it's always clear whether it is a HIGH or a LOW signal. However, the transition takes time. The delay introduced for the electronics to travel from a HIGH state to LOW takes place as shown in the below diagram.




The fall delay is the time taken for the transition from HIGH state to a LOW signal of any state. So when we see a clock working, we actually have a clock like this below.



To model these delays in Verilog, we use #NUMBER where NUMBER is the minimum number of clocks, the delay has to be made.

For example, if we make a simple code for AND gate, then the ideal gate would be coded as
and(C, A, B);   This represents C = A & B
However, with a delay in the circuit, we can code it as
and #1 (C, A, B): This too represents C = A & B but the output would have a delay of 1 tick of the clock.

Now each diagram above is a digital representation of a signal. What happens in the analog form is the most interesting part of signals. The analog form of the signal is the reason for Setup time and Hold time. When a signal is flipped to its complementary state, it takes time to stabilize. Until that time, the electronics oscillates in an undamped manner. This is called the switch Bouncing Effect. The following diagram would explain clearly.


Thus, the output clock edge must be captured and stabilized before any data change occurs. Now in Verilog, we use @posedge or @negedge for most sequential circuits. This means that the data has to undergo certain operations and produce an output during that change of transition, neither before, nor after. So the data is "held tightly" while the clock is transiting from the LOW state as we cannot afford the data to change before edge just because of some quantum disturbances. Now, as soon as the clock reaches midway, the change in data takes place and is again "held together" until the clock stabilizes its HIGH state.



As shown in the above diagram, during stabilization of clock, there are several "minute" positive and negative edge caused by oscillations which might trigger a change in the data if not held properly. It is this, why we require Setup Time and Hold Time.

To practice this in Verilog, we will execute some basic modules.

Code:
module Delay(A, B, C, D, E);
 input A,B;
 output C, D, E;
 wire p, q;


or #50 an2(q, A, B);
or #52 an3(p, A, B);
nand #54 an4(E, A, B);
assign C = p;
assign D = q;


endmodule

TestBench:
module TEst1;

reg A,B;
wire C,D,E;

Delay DEF(A, B, C, D,  E);

initial begin
A = 1;
B = 0;  
end
endmodule

OUTPUT with the delay for all changes


Here is an easy example to explain Rise delay.


Code:
module Delay(A, B, C, D, E);
 input A,B;
 output C, D, E;
 wire p, q;


or #2 an2(C, A, B);
or an3(D, A, B);
endmodule

TestBench:
module TEst1;

reg A,B;
wire C,D,E;

Delay DEF(A, B, C, D,  E);

initial begin
A = 1;
B = 0;  
        fork
       #10 A = 0; #B = 0;
end
endmodule

The signal D is driven without delay, hence it started the very moment, we started our simulation. It also changed its output when the inputs were changed at 10ns.
The signal C is driven by a delay of 2ns, hence it started with a delay of 2ns and also ended with a delay of 2ns. #NUM defines the delay where NUM is the delay of every parameter.

Now let us introduce, Rise delay and  Fall delay. Its basic syntax is:
#(R_Delay, F_Delay)

An example explaining both of these delay with comparison of no delay signal

Code:
module Delay(A, B, C, D, E);
 input A,B;
 output C, D, E;
 wire p, q;


or an2(q, A, B);
or #(2,0) an3(p, A, B);
or #(0,2) an4(E, A, B);

assign C = p;
assign D = q;
endmodule

TestBench:
module TEst1;

reg A,B;
wire C,D,E;

Delay DEF(A, B, C, D, E);

initial begin
A = 1;
B = 0;  
fork
#10 A = 0;
#10 B = 0;
join
end
endmodule

Output:

Now as shown in the code, signal C has a Rise delay of 2ns but no fall delay, hence it started at 2ns and not at 0ns but ended exactly at 10ns as we changed the signal exactly at 10ns. Thus without Fall delay, we didn't see the delay in C when the inputs were changed. The signal D, as usual, is having no delay hence it started and stopped without any delay. Signal E has no Rise delay, hence it started without any delay but it does have Fall delay, hence it ended with a delay of 2ns.

In the case of Turn Off delay, it is the minimum amount of time required to jump from X, 0, 1 to a high impedance state Z. Z is called the high impedance state. It signifies a connection split, hence the output has a very high resistance and is floating. Similarly, x signal has an unknown signal state.

Now, every signal has 3 delays with 3 sub delay for each delay. Confused? Me too.
We have 
1.)  Rise Delay 2.) Fall Delay 3.) Turn Off Delay
 Within the Rise/ fall/ turn-off delay, we have 3 subcategories.
  • Minimum Delay: This signifies the minimum amount of time delay to rise/ fall/ turn-off.
  • Typical Delay: This signifies the typical amount of time delay to rise/ fall/ turn-off.
  • Maximum Delay: This signifies the maximum amount of time delay to rise/ fall/ turn-off.
So now, we have to declare delay as follows:
#(min:typ:max, min:typ:max, min:typ:max)

Here is an example signifying the above:
Code:
module Delay(A, B, C, D, E);
 input A,B;
 output C, D, E;
 wire p, q;


or an2(q, A, B);
or #(0:2:4,2:3:4,1:2:3) an3(p, A, B);
or #(2:6:7) an4(E, A, B);

assign C = p;
assign D = q;
endmodule

TestBench:
module TEst1;

reg A,B;
wire C,D,E;

Delay DEF(A, B, C, D, E);

initial begin
A = 1;
B = 0;  
fork
#10 A = 0;
#10 B = 0;
join
end
endmodule

Output:



Here signal C is having a typical Rise delay of 2ns and typical Fall delay of 3ns.

Verilog simulation in Xilinx


Hi 
In this post, I am going to show you how to simulate a Verilog code in Xilinx ISE. I have included every step with an image so that the user can easily understand every step clearly. 

Ok let's begin 
I am using Xilinx ISE version 14.2 
You can have your own version of Xilinx or ModelSim or MultiSim HDL Simulator but the methodologies for implementing a Verilog code within them might be different. 

For this post its version 14.2 


First of all click on the desktop icon ISE Design Suite 14.2 



A Window will open. After the window opens, which might take some time depending on your system configuration. Click on the tab "New Project" as shown below. 



Enter the name of the project in the first field. Be sure that the location where you are going to save your project is having permission to write. You cannot save at a location that has only read only permission. 
Click "Next" and select the "Device" field as Spartan 6 because that's what I am going to use within this post.


Now click "Finish".

Now on the top left corner, you'll see two views. One of them states "Implementation" which is for finalizing implementing RTL schemaric of code and to find its parameters like heat, speeds, timings etc. The other view states "Simulation". We will start with the implementation first. Click on the  "Implementation" radio button 

Under your project name you will see another folder structure named xclscf something like that. Right click and click on new source.


Select "Verilog Module" and give the module a name. Click next when done. You can leave the input and output ports blank or you can enter the ports if you are sure about your code. As I am never sure of my code, I will leave it blank. I'll insert the input and output ports within the code itself.


For this post, I am implementing my own SPI which is the serial peripheral interface in this simulation. To have a look on my SPI simulation and code, Click Here.

A window on the right side will pop out as shown below. It will have some predefined comments, describing the date, user and creator of project. It's just the time and owner stamp. It's upto you whether you want to keep it or not.


I removed the time and creator stamp and pasted my own Master code from my SPI post. I have also added Slave code using the same method as I showed above to add a new "Verilog Module". Now its time to explain in layman terms about module, testbench, and datapath. I am expecting all students to have some classes about Verilog coding and understanding of wires, outputs, and circuits.

Let us consider an IC which has components like register file, multiplexors, adder, subtractor etc as shown below. 

As per the above diagram we have a component A and component B. 
For each component, as shown above, for A and for B, will have to declare a module or specifically saying a Verilog module like below. For module A, we are having an input present at pin 2 and an output present at pin 7. Similarly, for module B we have an input from pin 3 and from A and a single output at pin 6. The Verilog code for the module or the component a using the description above will be as follows

module A(in_pin2, out_pin7, out_to_B);
input in_pin2,
output out_pin7,
output out_to_B;
initial begin
<Code>
end
endmodule

module B(in_pin3, in_from_A, out_pin6);
input in_pin3,
input in_from_A,
output out_pin6,
initial begin
<Code>
end
endmodule

This is how we are going to add Verilog code for master as well as the slave for our simulation. 

No coming to the next question. What is a datapath?
Basically a data path includes the connection between various components inside the Integrated circuit. For example, in the above diagram, you can easily see components A and B are linked with each other using the red coloured wire and the wire which is attached to pin 7. Now, remember, for data path you have to include every wire that is connected between various models which are not present at the input or the output along with wires that you want to see as your output from the IC. 

All the connection between various models which are not the input port or the output port have to be declared as wires. In the above diagram,  component A has two internal wires with  the component B, the first one is the red wire and the second wire is connected with pin 7. Now I want to see the input of component A and component B as well as the output of component A and component B. 

module Datapath(in2,in3, out7, out6);
input int2, in3;
output out6, out7;
wire red_wire;
A Component_A(in2, out7, red_wire);
B Component_B(in3, red_wire, out6);
endmodule;

The basic syntax to instantiate a componet is 

Component Name Variable_Name (PORTS IN ORDER)

Here component name is A. Its variable name is "Component_A" and ports which have to be in order as they were declared in A. Have a close look at the ports of componet A within the brackets. 

(in_pin2, out_pin7, out_to_B);

The first port is in_pin2 which is an input pin attached to datapath port in2. The second port is out_pin7 which is connected to the out7 pin of the datapath. The third port is "out_to_B" which is an internal wire in datapath connected to "red_wire" in the datapath. One simply cannot assign any datapath port while instantiating a component. It has to be in order. Input port of IC is pin 2 which is declared as "in2" in the datapath. We have to connect this to component A's input which is "in_pin2" which is the first port declared within the brackets. Thus, while instantiating component A, we have to assign correct datapath port to the correct position of A. We cannot instantiate like this below

A Component_A(out7, in2, red_wire);

The first port of A, which is reserved to be input from pin 2 has to be the input from pin 2 but we have assigned "out7" to the input of A which is completely wrong. Similarly, we have assigned input from pin2 (in2) to the output of component A. The red wire is, however, assigned correctly to the 3rd position which points to output to B of A.


Now we have instantiated component A and component B within the data path, saving the data path module will automatically assign or basically put the module A and module B within the data path module. This shows that the models are being instantiated under the datapath module as shown in the below image. Now refer to the IC diagram above. As you can see, both the components lies within the IC. The IC is our datapath here hence, component A and B must lie within it.


Now coming to the tesbench part. A testbench is an environment which is used to provide input to our system and get the output from this system. Just take connecting a CRO to a transistor, where we can see the output from a transistor. Similarly, we can see our simulation through the testbench. One should always remember that all the input ports in the testbench have to be of Register type and all the outputs of have to be of wire type unlike in module where input has to be of wire type and the output can be wire as well as register.




To create a testbench, click on the "New source" and this time instead of selecting Verilog module select Verilog text fixture. It will show you some options of the available modules from your project on which you have to start your testing. We have to test the entire IC not specifically to the component A or component B. Select the data path module which is to be tested via Verilog text fixture or test bench. Xilinx will automatically assign ports according to the input and output ports defined in the data path module. Do remember that the internal wires are not attached with the testbench. The internal wire is that wire which is neither connected to the output nor to the input.
Only the input and the output of the data path will be connected to the test bench. All the input and output of the data path are the same to which we have to provide input and from which we have to derive the output. 

To simulate, we have to select the view "Simulation' which was earlier set to "Implementation". The moment you will set it to "Simulation", in the below menu you will get options like this.


Double click on "Behavioral Check Syntax" to check the logic for errors. Wish for a green colored tickmark beside. If successful, double-click on "Simulate Behavioral Model" to simulate and wait for the results. 


Now to see a specific port which is NOT present in the testbench can be selected from the leftmost panel from "Test" and "glbl" menu. Select the port and press CTRL + W and then "Re-Launch".

Regards