Gate Primitives

December 15, 2018 Shashi Suman 0 Comments

  


This page will describe GATE PRIMITIVES. These are used for synthesis in ASIC/FPGA tools and basically fits best for gate level simulation.

The first few primitives are

GATES
FUNCTIONS
NAND
Performs nand operation between two operands
NOR
Performs nor operation between two operands
OR
Performs or operation between two operands
AND
Performs and operation between two operands
XOR
Performs exor operation between two operands
XNOR
Performs exnor operation between two operands
NOT
Performs not operation between two operands



Here is the code that explains the above primitives.











The first letter within brackets is always an output and rest all are inputs.

Now I would show some transmission primitives.

GATES
FUNCTIONS
Not
Inverts the output
Bufif0
Passes the output if enable is low
Bufif1
Passes the output if enable is high
Notif0
Inverts value if enable is low
Notif1
Inverts value if enable is high
Buf
Passes the value


Code –




Output –







Switch Primitives

GATES
FUNCTIONS
Pmos
Single direction p-mos
Nmos
Single direction n-mos
Rpmos
Resistive function p-mos
Rnmos
Resistive function n-mos
Cmos
Single direction cmos(both p and n mos)
Rcmos
Resistive cmos
Pullup
Pulls up the resistor
Pulldown
Pulls down the resistor
Tranif0
Bidirectional transistor if threshold is low
Tranif1
Bidirectional transistor if threshold is high

All the switches pass from source to drain. Resistance will be introduced in R type primitives



Strength Values

Strength Value
SPECS
7
Supply Drive
6
Strong Pull
5
Pull Drive
4
Large Capacitance
3
Weak Drive
2
Medium Capacitance
1
Small Capacitance
0
High Impedance

Let us have two input buffers A and B and a single output C. A has Pull Drive (pull0) and B has Large Capacitance (large) then according to table Pull drive is stronger than Large capacitance. So the output C will be A since A is stronger than B.

Gate and Switching delays.

Verilog consists of certain types of delays associated with gates.
Among those are
·         Rise, fall, turn-off delays
·         Minimal, Typical and Maximum Delays
The RISE DELAY is associated with the change of 0,x,z to 1.
The FALL DELAY is associated with the change of 1,x,z to 0.
The TURN-OFF DELAY is associated with the change of 0,1,x to Z.
The MINIMUM DELAY is associated with minimum delay a gate can have.
The MAXIMUM DELAY is associated with maximum delay a gate can have.
The TYPICAL DELAY is associated with average delay a gate can have.



Here is delay code.










Output Waveform









Its clear output rises at 1ns as per rise delay and output d rises at typical rise delay of 2ns.


Minimum, Typical and Maximum delay are separated by : (colon). Rise, Turnoff and fall are separated by a comma.