### Verilog Code for MOD 6 Counter

As discussed in the previous post, I implemented the MOD 5 Counter. In this, I'll implement MOD 6 Counter. This counter will have 6 states starting from 000 to 101 and then again back to zero. However, according to the equation below,

N <= 2n
you might find it vague. Now, 6 is not a power of 2. So it is not as if it isn't possible to design a counter which will have a non-power of 2? We can certainly achieve this by using external circuitry, . With this type of counters, we will have D Flip-Flops with clear flags. By intuition, we can say that just after 101, we will have to somehow clear the flip-flops' values, thus bringing the values back to zero. To calculate the minimum number of gates, we will have to use the same equation.  This gives the value of n as 3. Hence, we will have to have 3 D flip-flops to count 6 states in order to satisfy the requirements of MOD 6 counter. Here, we will be using NAND gates to clear the flip-flops. For UP counters, we use Q output from each flip-flop. If we assign each bit of 101 to variables A, B, and C then we have to choose only those variables which are HIGH i.e. 1. Here we will choose A and C as both of these variables are 1. Only these variables will act as an input to the AND gate. When the state reaches 5 i.e. 101, NAND gate inputs will be 11 which will result in 0 and will be provided to each flip-flop. This will trigger the clear flag within each register, thus will reset each flip-flop to zero and counting of the states will start again.

Looks Tough huh?
Let us apply the concept to reality.

Our MOD 6 counter will count 6 states i.e. from 0 to 5 and then will reset the flip-flops back to zero. One can make a careful observation that the NAND gate that has been used must have some propagation delay. An ideal NAND gate would hang the counter onto a single state forever. The proposed counter is an asynchronous counter as each flip-flop is not simultaneously triggered and the clock is depended from the previous flip-flop.

Here is the Verilog code for the implementation:

Here is the output

Carefully Observe that the counter partially goes into the 6th state but resets itself. This delay is because of the NAND gate which takes time to compute the result. Here, have a look at the RTL schematic of the MOD 6 Counter.

In the Verilog code, I have introduced a delay of 1ns for the NAND gate. Try to set it to 0 and give it a shot. You might think that you would get an ideal MOD 6 counter but it won't happen. The system will hang at 110.

Why does it happen?

Well, it happens because of edge issue. In the Verilog code, observe the always condition. It says @(posedge clk or negedge clear), which means from state 101 as soon the second flip-flop goes from 0 to 1 to make the state 110 at the positive edge of the clock, the NAND gate with no delay will also turn on at the same instant. Thus counter stops as it cannot follow the two conditions at the same time. However, giving a delay will first activate the clock condition and then after the delay period arrives the clear edge which will reset the flip-flop again.

Problemo Solved!

1. Awesome. Thanks for this simple explanation

2. Please post the working as well for MOD 7 and MOD 9 counter as well

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5. please can you give the code and output for mod 6 asychonous using D flipflop