Showing posts from March, 2019

16-bit RISC Processor Verilog Code with Clock Gating

                    Clock Gating in 16-bit RISC Processor

Clock Gating is a technique where we provide a clock signal to a component or module only when it is needed. This is done to save power and only operate the running logic. This is mainly used in synchronous circuits. We can form a simple circuit of gating using AND gate. The output of AND gate must be connected to the ENABLE port of the microcontroller individual components. The first input of the AND gate will be the original clock signal being generated by the oscillator. The second input will be a control signal. 1 is the control signal, the module will be turned ON. 0 is the control signal, the module will be turned OFF.

Having ENABLE port is must to have in each of the components. Enable ports can be positive enable or negative enable. 0 will turn off the components having positive enable and 1 will turn off the components will negative enable. As per Wikipedia, this also helps to save die are on which the circuit is fabri…

Verilog Code of 16 Bit RISC Processor with working

Verilog Code for the 16 bit RISC Processor 
Hello Everyone, I know many of you out there have been waiting for the working code for this processor along with RTL Schematic. Well, I have successfully coded the single cycle processor with R format Instruction, I format and Branch instructions too. I'll start with my instruction first. It is 16 bit in length.
xxxx indicates the OPCODE which decides the operation which has to be carried out. yyyy indicates the location of Register 1. zzzz indicates the location of Register 2. qqqq indicates the location of Register where data has to be written. It also helps to determine the number of instructions the user wants to jump.
The code I have devised takes 5 clock cycles to execute a single instruction. For BRANCH format, I stall the processor for 1 clock cycle. So, to make it clear, we have 5 stages here,
1. Instruction Fetch Stage 2. Instruction Decode Stage 3. Arithmetic Stage 4. Memory Stage 5. Write Back St…

Verilog Code for I2C with RTL Schematic

Hi Guys,

Long time now. I was away dealing with my crappy life. Well, let's move to the main point as the title of this post suggests. This I2C is very much less complicated than all my previous I2C Verilog codes. The biggest surprise to my readers in this post is that this I2C has an RTL Schematic. I'll clear out everything about the code.

Let us begin.
I'll begin with the explanation of Master code first. I am assuming here that the readers have already read the I2C Basic post. If not then search this blog else move ahead.
In this I2C, I am assuming a few things. 1. It is a READ mode I2C only. No, Write mode. That would complicate a hell lot of stuff. 2. There is no malfunctioning with Master when it receives data from Slave, hence the acknowledge bit will be always 1(Not for Address matching).

What is in this I2C Code:
In this code, the master will send start bit and SCL will start. With this Master will start sending 7 bit Slave address. If the address does not match,…