16-bit RISC Processor Verilog Code with Clock Gating

                    Clock Gating in 16-bit RISC Processor

Clock Gating is a technique where we provide a clock signal to a component or module only when it is needed. This is done to save power and only operate the running logic. This is mainly used in synchronous circuits. We can form a simple circuit of gating using AND gate. The output of AND gate must be connected to the ENABLE port of the microcontroller individual components. The first input of the AND gate will be the original clock signal being generated by the oscillator. The second input will be a control signal. 1 is the control signal, the module will be turned ON. 0 is the control signal, the module will be turned OFF.

Having ENABLE port is must to have in each of the components. Enable ports can be positive enable or negative enable. 0 will turn off the components having positive enable and 1 will turn off the components will negative enable. As per Wikipedia, this also helps to save die are on which the circuit is fabricated. After all saving power is what we need.

This technique is mostly used in low power circuits which are intended to run from a 1.5V battery for a year. We can insert this technique via behavior modeling, RTL modeling. However, it is very important to verify the output as wrong switching of the clock will lead to the wrong supply of information and data. In my previous post, I had shared the RISC Processor code. without clock gating. The previous code has no enable ports on any components which inherently increases the power consumption if we can assume it virtually. The current code runs with GATING using AND gates. The Control Unit controls the gating signals for all the components. Control Unit receives clock signal all the time. The current code still has a clocked signal in the Control Unit. A further update might include some other logic. For now, let us understand this code.

Here is the RTL Schematic for the gating processor.

   Here is the screenshot of gating signals clocks of all components.

 In RTL Schematic you would observe that certain components are not connected/ wired. This is not an error but an optimization. When input or output does not change, it is taken as a constant by the simulator. Hence, it's wiring is trimmed. In the above RTL, the register file is an example. Now as per my previous post, each state will enable the clock for the next cycle. This will be controlled by the Control Unit. 

For example, in the below circuit, you can see clock gating.

Now the CU controls each AND gate to provide the clock to each component when needed. Now how our processor will work with GATING is as follows.

IM will switch clock for ID state and will turn off the switching for every other stage. In the ID stage, we will switch the clock for ALU stage and turn it off for other stages. When in the ALU stage, we switch clock for the MEM stage and turn it off for all other stages. When in the MEM stage, we will switch the clock for the WB stage and turn it off for other stages. When in the WB stage, we will switch clock for IM stage and ADDER stage and turn the clock off for other stages.

Code for 16-bit Gating Microcontroller (Pop Up Warning)Click here for Verilog Code
Below you can see the output of instruction not including BRANCH instructions as it wasn't fitting the screen. I would request users to decode and match the result and try to deduce what is happening in the processor, how output is being written in the registers etc.

and the beautiful gating clocks is here too.

Observe that after the MEM stage, we will have to clock the Register File to perform write step into write register. So after the MEM stage, we require clocking of Register File and Adder to.

Here is the power analysis of the above processor with GATING.

As per the analysis, my processor uses only 0.014 Watts. That's way less than the previous processor without GATING which was 0.089 Watts. This analysis is not recommended. I doubt whether it is correct or not. But for some minor assumptions I guess we can consider for a moment. Want some explanation about the result above or any other diagram? Comment !!


  1. Bro please upload verilog code of it

  2. Replies
    1. hello sir,
      i can't see the link for download

  3. hello sir,
    how do i test any program?
    is there any testbench that you have written to verify the functionality of the processor?

    1. Yes the code is already present in the post. Find the link.
      It has the code Nd testbench

    2. same problem sir..
      can't find the testbench..
      pls help....

  4. hello sir,
    Can this code be converted to 32/64 bit?

    1. Yes it can be converted to 32 to 64 bit. That will also increase opcodes

  5. sir,
    can u upload soft copy t0 refer how code is written and defination of each variable used within

  6. sir mux3 is missing in the link can u upload it

  7. Do you have the original RISC code with clock gating?
    I'd appreciate the comparison of before and after. Thank You


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