Showing posts from May, 2019

Verilog Code for 16 Bit MIPS Pipelined Processor

Hello everyone,

Long time no see. I was actually very busy with my job schedule and then also working on pipeline code. Well, I have successfully completed the pipelined version of the processor. I was working on32 bit but sadly, it had gotten corrupted and I was forced to work on 16 bit which I don't know why I don't like.
What is a pipelined processor?

Below is the processor in action. Be careful what data lines you chose for.

This is the datapath of the 5 stage processor. I might miss some wiring. Do comment if a genius mind finds something different from RTL when compared to the below datapath. If I will find some error, I will myself update it.

Pipelining is a methodology which helps us to parallelly process instructions and only passes that information which is required for the current instruction. If one remembers, that without pipelining when we had set the "regwrt" signal to 1. It will remain 1 until the write operation is complete. However, in pipelining i…